`timescale 10ns / 10ns
module flow_led_tb();

    reg clk_50m, rst_n;
    wire [3:0] led;

    initial begin
        $dumpfile("output/flow_led_tb.vcd");
        $dumpvars(0, flow_led_tb);
    end

    initial begin
        clk_50m = 0;
        rst_n = 0;
        #10 rst_n = 1;
        #100_000_000 $stop;
    end

    always #1 clk_50m <= ~clk_50m;

    flow_led flow_led_inst (
        .clk_50m        (clk_50m),
        .rst_n          (rst_n),
        .led            (led)
    );

endmodule  //flow_led_tb